About Velaura
Velaura is building the next generation of compute platforms for Physical AI.
As AI moves beyond the datacenter into robots, autonomous mobile systems, drones, and other embodied systems, traditional compute architectures are increasingly constrained by power, memory bandwidth, latency, real-time requirements, and functional safety considerations.
Our mission is to develop the foundational compute technologies that enable intelligent systems to operate efficiently in the physical world.
We are assembling a team of exceptional architects and engineers to rethink how AI, sensing, memory, and control interact within a modern computing platform.
The Role
We are looking for talented Design Verification Engineers to help verify and deliver Velaura’s next-generation Physical AI SoC.
In this role, you will work closely with architects, RTL engineers, software engineers, and system teams to verify complex hardware blocks and system-level behavior across the entire platform.
You will help establish confidence in the correctness, performance, reliability, and safety of the architecture—from individual RTL blocks to complete HW/SW systems running real-world workloads.
We welcome engineers at all experience levels who enjoy understanding systems, finding corner cases, and solving challenging technical problems.
Responsibilities
- Develop and execute verification strategies for key portions of the Velaura SoC.
- Build verification environments using SystemVerilog, UVM, assertions, formal verification, emulation, and related methodologies.
- Collaborate with architects and RTL engineers to define verification plans, coverage goals, and correctness criteria.
- Verify compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, and other critical SoC infrastructure.
- Perform HW/SW co-verification involving firmware, drivers, runtime software, and operating system interactions.
- Verify performance, latency, bandwidth, QoS, and real-time system behavior under representative workloads.
- Develop assertions, checkers, scoreboards, and automated verification infrastructure.
- Participate in emulation, FPGA prototyping, and pre-silicon software bring-up activities.
- Drive bug investigation, root-cause analysis, and debug across hardware and software boundaries.
- Leverage modern engineering tools, including AI-assisted verification workflows, to improve productivity, quality, and coverage.
- Contribute to a culture of technical excellence and continuous improvement.
Desired Experience
- Experience verifying complex digital systems.
- Strong understanding of computer architecture, microarchitecture, and digital design fundamentals.
- Experience with SystemVerilog, UVM, assertions, coverage-driven verification, and related methodologies.
- Familiarity with formal verification techniques and tools.
- Experience with emulation, FPGA prototyping, or pre-silicon validation environments.
- Understanding of memory systems, interconnect fabrics, caches, DMA engines, processors, or accelerator architectures.
- Experience debugging complex system-level issues.
- Strong analytical and problem-solving skills.
- Ability to work effectively in a collaborative, multidisciplinary engineering environment.
Relevant Backgrounds
- CPUs
- GPUs
- AI accelerators
- Networking and communications silicon
- Storage and data movement architectures
- Robotics and autonomous systems
- Automotive and ADAS platforms
- Aerospace and defense systems
- Real-time and safety-critical computing
- Functional safety architectures and methodologies
Functional Safety Experience
Experience with one or more of the following standards is a plus:
- ISO 26262
- IEC 61508
- IEC 61511
- ISO 13849
Nice to Have
- Experience with AI, machine learning, or edge AI hardware.
- Familiarity with robotics, drones, autonomous vehicles, or industrial automation systems.
- Experience verifying QoS, latency-sensitive, or real-time systems.
- Experience with HW/SW co-verification and system-level validation.
- Exposure to performance modeling, profiling, and workload characterization.
- Experience using modern AI tools and workflows to accelerate engineering productivity.
Why Velaura?
This is an opportunity to help verify a new class of computing architecture at a time when the industry is undergoing fundamental change.
You will work alongside experienced leaders and architects who have delivered industry-defining products across mobile, cloud, and AI platforms.
Most importantly, you will help answer not only whether the design works, but whether it behaves correctly under the complex, real-time, and safety-critical workloads required by the next generation of Physical AI systems.
If you enjoy understanding systems, finding the bugs others miss, and helping shape the future of Physical AI, we would love to hear from you.